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ISL54205A
Data Sheet December 7, 2006 FN6342.1
MP3/USB 2.0 High Speed Switch with Negative Signal Handling
The Intersil ISL54205A dual SPDT (Single Pole/Double Throw) switches combine low distortion audio and accurate USB 2.0 high speed data (480Mbps) signal switching in the same low voltage device. When operated with a 2.7V to 3.6V single supply these analog switches allow audio signal swings below-ground, allowing the use of a common USB and audio headphone connector in Personal Media Players and other portable battery powered devices. The ISL54205A incorporates circuitry for detection of the USB VBUS voltage, which is used to switch between the audio and USB signal sources in the portable device. The part has a control pin to open all the switches and put the part in a low power down state. The ISL54205A is available in a small 10 Ld 2.1mm x 1.6mm ultra-thin TQFN package and a 10Ld 3mm x 3mm TDFN package. It operates over a temperature range of -40 to +85C.
Features
* High Speed (480Mbps) Signaling Capability per USB 2.0 * Low Distortion Negative Signal Capability * Detection of VBUS Voltage on USB Cable * Control Pin to Open all Switches and Enter Low Power State * Low Distortion Headphone Audio Signals - THD+N at 20mW into 32 Load . . . . . . . . . . . . . <0.1% * Cross-talk (20Hz to 20kHz) . . . . . . . . . . . . . . . . . . -110dB * Single Supply Operation (VDD) . . . . . . . . . . . . 2.7V to 3.6V * -3dB Bandwidth USB Switch . . . . . . . . . . . . . . . . . 630MHz * Available in TQFN and TDFN Packages * Pb-Free Plus Anneal (RoHS Compliant) * Compliant with USB 2.0 Short Circuit Requirements Without Additional External Components
Applications Related Literature
* Application Note AN1280 "ISL54205EVAL1Z Evaluation Board User's Manual. * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches" * MP3 and Other Personal Media Players * Cellular/Mobile Phones * PDA's * Audio/USB Switching
Application Block Diagram
VDD VBUS USB/HEADPHONE JACK 22k COM D+ ISL54205A CTRL Logic Circuitry 4M 4M DUSB HIGH-SPEED TRANSCEIVER CONTROLLER
COM +
50k
L R CODEC
50k
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54205A Pinouts
(Note 1) ISL54205A (10 LD TQFN) TOP VIEW
CTRL 10 4M 9 8 7 6 50k 5 GND 50k DD+ L R VDD VBUS COM 1 2 4M 3 4 5 50k 50k LOGIC CONTROL 10 9 8 7 6 CTRL DD+
ISL54205A (10 LD TDFN) TOP VIEW
4M
VDD VBUS COM -
1 2 3 4
LOGIC CONTROL 4M
COM + GND
L R
COM +
NOTE: 1. ISL54205 Switches shown for VBUS = Logic "0" and CTRL = Logic "1".
Truth Table
ISL54205A VBUS 0 0 1 CTRL 0 1 X L, R OFF ON OFF D+, DOFF OFF ON
Pin Descriptions
ISL54205A PIN NO. 1 2 3 4 5 6 NAME VDD VBUS COMCOM+ GND R L D+ DCTRL Power Supply Digital Control Input Voice and Data Common Pin Voice and Data Common Pin Ground Connection Audio Right Input Audio Left Input USB Differential Input USB Differential Input Digital Control Input (Audio Enable) FUNCTION
CTRL: Logic "0" when 0.5V, Logic "1" when 1.4V VBUS: Logic "0" when VDD + 0.2V or Floating, Logic "1" when VDD + 0.8V
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. #
7 8 9 10
ISL54205AIRUZ-T FT (Note) ISL54205AIRZ-T (Note) ISL54205AIRZ (Note) ISL54205EVAL1Z 205Z
-40 to +85 10 Ld TQFN L10.2.1x1.6A Tape and Reel (Pb-free) L10.3x3A -40 to +85 10 Ld TDFN Tape and Reel (Pb-free) -40 to +85 10 Ld TDFN (Pb-free) L10.3x3A
205Z
-40 to +85 Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate or NiPdAu termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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ISL54205A
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V Input Voltages D+, D-, L, R (Note 2) . . . . . . . . . . . . . . . . . - 2V to ((VDD) + 0.3V) VBUS (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 5.5V CTRL (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V) Output Voltages COM-, COM+ (Note 2) . . . . . . . . . . . . . . . . -2V to ((VDD) + 0.3V) Continuous Current (Audio Switches). . . . . . . . . . . . . . . . . 150mA Peak Current (Audio Switches) (Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . 300mA Continuous Current (USB Switches). . . . . . . . . . . . . . . . . . . 40mA Peak Current (USB Switches) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA ESD Rating: HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >7kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >450V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV
Thermal Information
Thermal Resistance (Typical, Note 3) 10 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . . 10 Ld 3x3 TDFN Package. . . . . . . . . . . . . . . . . . . . . JA (C/W) 130 110
Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range. . . . . . . . . . . . -65C to +150C
Operating Conditions
Temperature Range ISL54205AIRUZ and ISL54205AIRZ . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on D+, D-, L, R, COM-, COM+, CTRL, VBUS exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V,
VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 4, 6), unless otherwise specified. TEMP (C) MIN (Note 5) MAX (Note 5)
PARAMETER ANALOG SWITCH CHARACTERISTICS Audio Switches (L, R) Analog Signal Range, VANALOG ON Resistance, rON
TEST CONDITIONS
TYP
UNITS
VDD = 3.0V, VBUS = float, CTRL = 1.4V VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = -0.85V to 0.85V, (See Figure 3) VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = Voltage at max rON over signal range of -0.85V to 0.85V, (Note 9) VDD = 3.0V, VBUS = float, CTRL = 1.4V, ICOMx = 100mA, VL or VR = -0.85V to 0.85V, (Note 7) VDD = 3.6V, VBUS = float, CTRL = 1.4V, VCOM- or VCOM+ = -0.85V, 0.85V, VL or VR = -0.85V, 0.85V, VD+ and VD- = floating, Measure current through the discharge pull-down resistor and calculate resistance value.
Full +25 Full +25 Full +25 Full +25
-1.5 -
2.65 0.02 0.03 50
1.5 4 5.5 0.13 0.16 0.05 0.07 -
V k
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
Discharge Pull-Down Resistance, RL, RR
USB Switches (D+, D-) Analog Signal Range, VANALOG ON Resistance, rON VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = 0V to 400mV (See Figure 4) VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = Voltage at max rON, (Note 8) Full +25 Full +25 Full 0 4.6 0.06 VDD 5 6.5 0.5 0.55 V
rON Matching Between Channels, rON
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ISL54205A
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V,
VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 4, 6), unless otherwise specified. (Continued) PARAMETER rON Flatness, RFLAT(ON) TEST CONDITIONS VDD = 3.6V, VBUS = 4.4V, CTRL = 0V or 3.6V, ICOMx = 40mA, VD+ or VD- = 0V to 400mV, (Note 7) VDD = 3.6V, VBUS = 0V, CTRL = 3.6V, VCOM- or VCOM+ = 0.5V, 0V, VD+ or VD- = 0V, 0.5V, VL and VR = float VDD = 3.3V, VBUS = 5.25V, CTRL = 0V or 3.6V, VD+ or VD- = 2.0V, VCOM-,VCOM+, VL and VR = float TEMP (C) +25 Full +25 Full +25 Full MIN (Note 5) -10 -70 -10 -75 TYP 0.4 2 MAX (Note 5) 0.6 1.0 10 70 10 75 UNITS nA nA nA nA
OFF Leakage Current, ID+(OFF) or ID-(OFF) ON Leakage Current, IDx
DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Break-Before-Make Time Delay, tD Skew, tSKEW VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 1) VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 1) VDD = 2.7V, RL = 50, CL = 10pF, (See Figure 2) VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 45, CL = 10pF, tR = tF = 720ps at 480Mbps, (Duty Cycle = 50%) (See Figure 7) VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 50, CL = 10pF, tR = tF = 750ps at 480Mbps VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, RL = 45, CL = 10pF, (See Figure 7) VDD = 3.0V, VBUS = float, CTRL = 3.0V, RL = 32, f = 20Hz to 20kHz, VR or VL = 0.707VRMS (2VP-P), (See Figure 6) f = 20Hz to 20kHz, VDD = 3.0V, VBUS = float, CTRL = 3.0V, VL or VR = 0.707VRMS (2VP-P), RL = 32 Signal = 0dBm, 0.2VDC offset, RL = 50, CL = 5pF +25 +25 +25 +25 67 48 18 50 ns ns ns ps
Total Jitter, tJ Propagation Delay, tPD Crosstalk (Channel-to-Channel), R to COM-, L to COM+ Total Harmonic Distortion USB Switch -3dB Bandwidth
+25 +25 +25
-
210 250 -110
-
ps ps dB
+25 +25 +25 +25 +25
-
0.06 630 6 9 10
-
% MHz pF pF pF
D+/D- OFF Capacitance, CD+(OFF), f = 1MHz, VDD = 3.0V, VBUS = float, CTRL = 3.0V, CD-(OFF) VD- or VD+ = VCOMx = 0V, (See Figure 5) L/R OFF Capacitance, CLOFF, CROFF f = 1MHz, VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, VL or VR = VCOMx = 0V, (See Figure 5)
COM ON Capacitance, CCOM-(ON), f = 1MHz, VDD = 3.0V, VBUS = 5.0V, CTRL = 0V or 3V, CCOM+(ON) VD- or VD+ = VCOMx = 0V, (See Figure 5) POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 3.6V, VBUS = float or 5.25V, CTRL = 1.4V
Full +25 Full
2.7 6 1 -
3.6 8 10 7 140
V A A nA nA
Positive Supply Current, IDD (Low Power State)
VDD = 3.6V, VBUS = 0V or float, CTRL = 0V or float
+25 Full
DIGITAL INPUT CHARACTERISTICS VBUS Voltage Low, VBUSL VBUS Voltage High, VBUSH CTRL Voltage Low, VCTRLL CTRL Voltage High, VCTRLH Input Current, IBUSL, ICTRLL VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V VDD = 2.7V to 3.6V VDD = 3.6V, VBUS = 0V or float, CTRL = 0V or float Full Full Full Full Full VDD + 0.8 1.4 -50 20 VDD + 0.2 0.5 50 V V V V nA
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FN6342.1 December 7, 2006
ISL54205A
Electrical Specifications - 2.7V to 3.6V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V,
VCTRLH = 1.4V, VCTRLL = 0.5V, (Notes 4, 6), unless otherwise specified. (Continued) PARAMETER Input Current, IBUSH Input Current, ICTRLH VBUS Pull-Down Resistor, RVBUS CTRL Pull-Down Resistor, RCTRL NOTES: 4. VLOGIC = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Guaranteed by design. 9. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between L and R or between D+ and D-. TEST CONDITIONS VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V VDD = 3.6V, VBUS = 5.25V, CTRL = 0V or float VDD = 3.6V, VBUS = 0V or float, CTRL = 3.6V TEMP (C) Full Full Full Full MIN (Note 5) -2 -2 TYP 1.1 1.1 4 4 MAX (Note 5) 2 -2 UNITS A A M M
Test Circuits and Waveforms
VBUSH LOGIC INPUT VBUSL 50% tr < 20ns tf < 20ns VDD C
tOFF SWITCH INPUT VINPUT 90% SWITCH OUTPUT 0V tON VOUT 90% VBUS SWITCH INPUT
CTRL VINPUT AUDIO OR USB COMX VBUS GND RL 50 CL 10pF VOUT
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray RL capacitance. V OUT = V (INPUT) --------------------------R +r
L ( ON )
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
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FN6342.1 December 7, 2006
ISL54205A Test Circuits and Waveforms (Continued)
VDD C
VBUSH LOGIC INPUT VBUSL VINPUT L or R VOUT SWITCH OUTPUT 0V tD 90% VBUS VBUS GND RL 50 CL 10pF CTRL D- or D+ COMx VOUT
Repeat test for all switches. CL includes fixture and stray capacitance.
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME
FIGURE 2B. TEST CIRCUIT
VDD C
VDD C
rON = V1/100mA
L OR R
rON = V1/40mA CTRL VD- or D+ VBUS OV OR FLOAT V1 40mA
COMX COMx
CTRL
D- or D+
VL OR R V1 100mA GND
VBUS 4.4V to 5.25V
GND
Repeat test for all switches.
Repeat test for all switches.
FIGURE 3. AUDIO rON TEST CIRCUIT
FIGURE 4. USB rON TEST CIRCUIT
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FN6342.1 December 7, 2006
ISL54205A Test Circuits and Waveforms (Continued)
VDD C VDD C
CTRL
AUDIO OR USB
CTRL SIGNAL GENERATOR
L or R COMx
32
VBUS IMPEDANCE ANALYZER
COMx
VBUS VBUSL or VBUSH 0V or Float
GND
ANALYZER RL
COMx
R or L
GND
N.C.
Repeat test for all switches.
Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches.
FIGURE 5. CAPACITANCE TEST CIRCUIT
FIGURE 6. AUDIO CROSSTALK TEST CIRCUIT
VDD tri 90% DIN+ DIN90% 50% 10% tfi tro 90% 10% OUT+ OUT90% tf0 50% tskew_o 50% 10% GND DIN143 10% 50% tskew_i DIN+ 143 15.8 COMVBUSH 15.8 CTRL VBUS COM+
C
D+ CL DCL
OUT+ 45 OUT45
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals.
FIGURE 7A. MEASUREMENT POINTS FIGURE 7. SKEW TEST
FIGURE 7B. TEST CIRCUIT
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FN6342.1 December 7, 2006
ISL54205A Application Block Diagram
VDD VBUS USB/HEADPHONE JACK 22k COM D+ ISL54205A CTRL LOGIC CIRCUITRY 4M 4M DUSB HIGH-SPEED TRANSCEIVER CONTROLLER
COM +
50k
L R CODEC
50k
GND
Detailed Description
The ISL54205A device is a dual single pole/double throw (SPDT) analog switch device that operates from a single DC power supply in the range of 2.7V to 3.6V. It was designed to function as a dual 2 to 1 multiplexer to select between USB differential data signals and audio L and R stereo signals. It comes in tiny TQFN and TDFN packages for use in MP3 players, PDAs, cell phones, and other personal media players. The part consists of two 3 audio switches and two 5 USB switches. The audio switches can accept signals that swing below ground. They were designed to pass audio left and right stereo signals, that are ground referenced, with minimal distortion. The USB switches were designed to pass highspeed USB differential data signals with minimal edge and phase distortion. The ISL54205A was specifically designed for MP3 players, cell phones and other personal media player applications that need to combine the audio headphone jack and the USB data connector into a single shared connector, thereby saving space and component cost. A typical application block diagram of this functionality is shown above. The ISL54205A incorporates circuitry for the detection of the USB VBUS voltage, which is used to switch between the audio CODEC drivers and USB transceiver of the MP3 player or cell phone. The ISL54205A contains a logic control pin (CTRL) that when driven Low while VBUS is Low, opens all switches and puts the part into a low power state, drawing typically 1nA of IDD current. A detailed description of the two types of switches is provided in the sections below. The USB transmission and audio playback are intended to be mutually exclusive operations.
Audio Switches
The two audio switches (L, R) are 3 switches that can pass signals that swing below ground. Crosstalk between the audio switches over the audio band is < -110dB. Over a signal range of 1V (0.707Vrms) with VDD >2.7V, these switches have an extremely low rON resistance variation. They can pass ground referenced audio signals with very low distortion (<0.06% THD+N) when delivering 15.6mW into a 32 headphone speaker load. See Figures 8, 9, 10, and 11 THD+N performance curves. These switches are uni-directional switches. The audio drivers should be connected at the L and R side of the switch (pins 7 and 8) and the speaker loads should be connected at the COM side of the switch (pins 3 and 4). The audio switches are active (turned ON) whenever the VBUS voltage is to VDD + 0.2V or floating and the CTRL voltage to 1.4V. Note: Whenever the audio switches are ON the USB transceivers need to be in the high impedance state or static high or low state.
USB Switches
The two USB switches (D+, D-) are 5 bidirectional switches that are designed to pass high-speed USB differential signals in the range of 0V to 400mV. The switches have low capacitance and high bandwidth to pass USB high-speed signals (480Mbps) with minimum edge and phase distortion to meet USB 2.0 signal quality specifications. See Figure 12 for High-speed Eye Pattern taken with switch in the signal path. The maximum signal range for the USB switches is from -1.5V to VDD. The signal voltage at D- and D+ should not be allowed to exceed the VDD voltage rail or go below ground by more than -1.5V.
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FN6342.1 December 7, 2006
ISL54205A
The USB switches are active (turned ON) whenever the VBUS voltage is to VDD + 0.8V. VBUS is internally pulled low, so when VBUS is floating, the USB switches are OFF. Note: Whenever the USB switches are ON the audio drivers of the CODEC need to be at AC or DC ground or floating to keep from interfering with the data transmission. Low Power Mode If the VBUS pin = Logic "0" and CTRL pin = Logic "0," the part will be in the Low Power mode. In the Low Power mode, the audio switches and the USB switches are OFF (high impedance). In this state, the device draws typically 1nA of current. EXTERNAL VBUS SERIES RESISTOR The ISL54205A contains a clamp circuit between VBUS and VDD. Whenever the VBUS voltage is greater than the VDD voltage by more than 2.55V, current will flow through this clamp circuitry into the VDD power supply bus. During normal USB operation, VDD is in the range of 2.7V to 3.6V and VBUS is in the range of 4.4V to 5.25V. The clamp circuit is not active and no current will flow through the clamp into the VDD supply. In a USB application, the situation can exist where the VBUS voltage from the computer could be applied at the VBUS pin before the VDD voltage is up to its normal operating voltage range and current will flow through the clamp into the VDD power supply bus. This current could be quite high when VDD is OFF or at 0V and could potentially damage other components connected in the circuit. In the application circuit, a 22k resistor has been put in series with the VBUS pin to limit the current to a safe level during this situation. It is recommended that a current limiting resistor in the range of 10k to 50k be connected in series with the VBUS pin. It will have minimal impact on the logic level at the VBUS pin during normal USB operation and protect the circuit during the time VBUS is present before VDD is up to its normal operating voltage. Note: No external resistor is required in applications where VBUS will not exceed VDD by more than 2.55V. POWER The power supply connected at VDD (pin 1) provides power to the ISL54205A part. Its voltage should be kept in the range of 2.7V to 3.6V when used in a USB/Audio application to ensure you get proper switching when the VBUS voltage is at its lower limit of 4.4V.
ISL54205A Operation
The discussion that follows will discuss using the ISL54205A in the typical application shown in the block diagram on page 8. LOGIC CONTROL The state of the ISL54205A device is determined by the voltage at the VBUS pin (pin 2) and the CTRL pin (pin 10). Refer to truth-table on page 2 of data sheet. The VBUS pin and CTRL pin are internally pulled low through 4M resistors to ground and can be left floating. The CTRL control pin is only active when VBUS is logic "0". Logic control voltage levels: VBUS = Logic "0" (Low) when VBUS VDD + 0.2V or Floating. VBUS = Logic "1" (High) when VBUS VDD + 0.8V CTRL = Logic "0" (Low) when 0.5V or floating. CTRL = Logic "1" (High) when 1.4V Audio Mode If the VBUS pin = Logic "0" and CTRL pin = Logic "1," the part will be in the Audio mode. In Audio mode the L (left) and R (right) 3 audio switches are ON and the D- and D+ 5 switches are OFF (high impedance). In a typical application, VDD will be in the range of 2.7V to 3.6V and will be connected to the battery or LDO of the MP3 player or cell phone. When a headphone is plugged into the common connector, nothing gets connected at the VBUS pin (it is floating) and as long as the CTRL = Logic "1," the ISL54205A part remains in the audio mode and the audio drivers of the player can drive the headphones and play music. USB Mode If the VBUS pin = Logic "1" and CTRL pin = Logic "0" or Logic "1," the part will go into USB mode. In USB mode, the D- and D+ 5 switches are ON and the L and R 3 audio switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common connector, the voltage at the VBUS pin will be driven to be in the range of 4.4V to 5.25V. The ISL54205A part will go into the USB mode. In USB mode, the computer or USB hub transceiver and the MP3 player or cell phone USB transceiver are connected and digital data will be able to be transmitted back and forth. When the USB cable is disconnected, the ISL54205A automatically turns the D+ and D- switches OFF.
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Typical Performance Curves TA = +25C, Unless Otherwise Specified
0.11 RLOAD = 32 VLOAD = 0.707VRMS 0.3 VDD = 2.6V THD+N (%) 0.08 THD+N (%) 0.4 RLOAD = 32 VDD = 3V 3VP-P 0.10
0.09
0.2 2.5VP-P 0.1 2VP-P 1VP-P 20 200 2k FREQUENCY (Hz) 20k
0.07 VDD = 2.7V 0.06 VDD = 3V VDD = 3.6V
0.05
0.04 20 200 2k FREQUENCY (Hz) 20k
0
FIGURE 8. THD+N vs SUPPLY VOLTAGE vs FREQUENCY
FIGURE 9. THD+N vs SIGNAL LEVELS vs FREQUENCY
0.5 RLOAD = 32 FREQ = 1kHz VDD = 3V
0.5 RLOAD = 32 FREQ = 1kHz VDD = 3V
0.4
0.4
THD+N (%)
0.2
THD+N (%)
0.3
0.3
0.2
0.1
0.1
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (VP-P)
0 0 10 20 30 40 50 OUTPUT POWER (mW)
FIGURE 10. THD+N vs OUTPUT VOLTAGE
FIGURE 11. THD+N vs OUTPUT POWER
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FN6342.1 December 7, 2006
ISL54205A Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
VOLTAGE (835mV/DIV)
TIME (10ns/DIV)
FIGURE 12. EYE PATTERN: 480Mbps WITH SWITCH IN THE SIGNAL PATH
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FN6342.1 December 7, 2006
ISL54205A Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
1 USB SWITCH 0
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND
-1 NORMALIZED GAIN (dB) -2
TRANSISTOR COUNT:
-3 -4
98 PROCESS: Submicron CMOS
RL = 50 VIN = 0.2VP-P to 2VP-P 1M 10M 100M FREQUENCY (Hz) 1G
FIGURE 13. FREQUENCY RESPONSE
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FN6342.1 December 7, 2006
ISL54205A Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.2.1x1.6A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 2.05 1.55 0.20 2.10 1.60 0.50 BSC 0.20 0.35 0.40 10 4 1 0 12 0.45 0.25 2.15 1.65 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. Same as JEDEC MO-255UABD except: No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm "L" MAX dimension = 0.45 not 0.42mm. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
2.50 1.75
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW (DATUM A) PIN #1 ID 1 2 NX L N (DATUM B) N-1 e 3 (ND-1) X e BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e (A1) NX b 5 A
C
D E e k L N
4xk
Nd Ne
0.10 M C A B 0.05 M C
L
TERMINAL TIP
FOR ODD TERMINAL/SIDE
b
0.05 MIN
L 2.00 0.80
0.275
0.10 MIN DETAIL "A" PIN 1 ID 0.50
0.25
LAND PATTERN 10
13
FN6342.1 December 7, 2006
ISL54205A Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// A 0.10 C 0.08 C
0.20 2.95 2.25 2.95 1.45
0.25 3.0 2.30 3.0 1.50 0.50 BSC
0.30 3.05 2.35 3.05 1.55
5, 8 7, 8 7, 8 -
E2 e k
0.25 0.25
0.30 10 5
0.35
8 2 3 Rev. 3 3/06
C SEATING PLANE
SIDE VIEW
A3
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L1 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6342.1 December 7, 2006

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